1. Field of the Invention
The present invention relates generally to methods for forming metal oxide layers within fabrications including but not limited to as microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced compositional purity, metal oxide layers within fabrications including but not limited to microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased, and more particularly as semiconductor integrated circuit microelectronic fabrication integration levels have increased, there has evolved a continuing and correlating trend towards decreased linewidth dimensions and decreased thickness dimensions of microelectronic layers that are employed when fabricating microelectronic devices and microelectronic structures employed in fabricating microelectronic fabrications.
Of the microelectronic layers whose thicknesses have traditionally decreased when fabricating advanced microelectronic fabrications, and whose thickness uniformity and materials composition integrity is generally of considerable importance when fabricating microelectronic fabrications, are capacitive dielectric layer which are conventionally employed as: (1) gate dielectric layers within field effect transistors (FETs) within semiconductor integrated circuit microelectronic fabrications; as well as (2) capacitor plate separation dielectric layers within various types of capacitors within various types of microelectronic fabrications, including but not limited to semiconductor integrated circuit microelectronic fabrications.
While continuing decreases in thickness of capacitive dielectric layers are generally desirable in the art of microelectronic fabrication in order to theoretically provide enhanced performance of capacitive devices within advanced microelectronic fabrications, there nonetheless exist considerable technical barriers to forming, with both decreased thickness and enhanced compositional Integrity, capacitive dielectric layers of conventional dielectric materials, such as silicon oxide dielectric materials, silicon nitride dielectric materials, silicon oxynitride dielectric materials and composites thereof, such as to provide enhanced performance of capacitive devices within advanced microelectronic fabrications, and in particular enhanced performance of capacitive devices within advanced semiconductor integrated circuit microelectronic fabrications.
In an effort to provide enhanced performance of capacitive devices within advanced microelectronic fabrications while avoiding decreased thicknesses of capacitive dielectric layers within the capacitive devices, there has been proposed in the alternative of employing conventional silicon oxide dielectric materials, silicon nitride dielectric materials, silicon oxynitride dielectric materials and composites thereof when forming capacitive dielectric layers within advanced microelectronic fabrication, to employ dielectric materials having generally higher dielectric constants, typically and preferably in a range of from about 10 to about 30 (in comparison with a range of from about 4 to about 8 for conventional silicon oxide dielectric materials, silicon nitride dielectric materials, silicon oxynitride dielectric materials and composites thereof). Such dielectric materials having generally higher dielectric constants allow for increased thicknesses of capacitive dielectric layers while simultaneously providing for enhanced capacitive properties of capacitive devices when fabricating microelectronic fabrications. Of the higher dielectric constant dielectric materials that have been proposed for use when forming capacitive dielectric layers within capacitive devices within advanced microelectronic fabrications, alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials (i.e., metal silicate dielectric materials), as well as derivatives thereof, are presently of considerable interest.
While alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, are thus desirable in the art of microelectronic fabrication for use when forming capacitive dielectric layers within capacitive devices within microelectronic fabrications, alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, are similarly nonetheless also not entirely without problems in the art of microelectronic fabrication when forming capacitive dielectric layers within capacitive devices within microelectronic fabrications. In that regard, it is often difficult to form alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, with enhanced compositional purity when forming a capacitive dielectric layer within a capacitive device within a microelectronic fabrication, particularly when employing for forming the alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, chemical vapor deposition (CVD) methods, and in particular chemical vapor deposition (CVD) methods that employ metal and carbon containing source materials, such as but not limited to organometallic (i.e., metal-carbon bonded) metal and carbon containing source materials.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials for forming, with enhanced compositional purity, alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, and derivatives thereof, for use when forming capacitive dielectric layers within capacitive devices within microelectronic fabrications.
It is towards the foregoing object that the present invention is more specifically directed.
Various methods and materials have been disclosed within arts including but not limited to microelectronic fabrication arts, for forming substrates and layers, such as but not limited to microelectronic fabrication substrates and microelectronic fabrication layers, with desirable properties within arts including but not limited to microelectronic fabrication arts.
For example, Jelks, in U.S. Pat. No. 4,505,949, discloses a method for forming within a microelectronic fabrication a microelectronic layer upon a microelectronic substrate while avoiding when forming the microelectronic layer upon the microelectronic substrate use of an extrinsic toxic gaseous microelectronic layer source material. To realize the foregoing object, the method comprises a two step method wherein: (1) a first step within the two step method employs an in-situ upstream plasma etching of a solid microelectronic layer source material target to form an intrinsic gaseous microelectronic layer source material; and (2) a second step within the two step method employs an in-situ downstream decomposition, preferably an in-situ downstream laser initiated decomposition, of the intrinsic gaseous microelectronic layer source material, to form the microelectronic layer upon the microelectronic substrate.
In addition, Callegari et al., in xe2x80x9cDUV stability of carbon films for attenuated phase shift mask applications,xe2x80x9d SPIE 23rd Annual International Symposium on Microlithography, Santa Clara, Calif., Feb. 22-27, 1998, discloses a method for fabricating within an attenuated phase shift mask fabrication an amorphous carbon layer for use as a semitransparent shifter layer within the attenuated phase shift mask fabrication, such that the attenuated phase shift mask fabrication is stable upon deep ultraviolet irradiation within an oxygen containing ambient environment (i.e., under conventional photoexposure conditions to which the attenuated phase shift mask fabrication is exposed). To realize the foregoing object, the method employs a reactive sputtering method that in turn employs: (1) a graphite sputtering target; (2) an argon/hydrocarbon reactant gas composition; and (3) a phase shift mask substrate held at a radio frequency bias potential, when forming the amorphous carbon layer within the attenuated phase shift mask fabrication.
Further, Elliott et al., in U.S. Pat. No. 5,669,979 and U.S. Pat. No. 5,814,156, disclose: (1) a method for removing from a substrate employed within a fabrication including but not limited to a microelectronic fabrication; and (2) an apparatus for removing from the substrate employed within the fabrication including but not limited to the microelectronic fabrication, a contaminant layer, such as but not limited to a ion implanted photoresist mask layer contaminant layer. To realize the foregoing object, the method and the apparatus employ a simultaneous ultraviolet laser irradiation of the contaminant layer in the presence of a reactive gas while employing conditions which photo-facilitate a chemical reaction which removes from the substrate the contaminant layer.
Yet further, Morinville et al., in U.S. Pat. No. 5,709,754, discloses an analogous method and an analogous apparatus for removing from a substrate, and in particular a microelectronic fabrication substrate, a photoresist layer employed in fabricating the substrate. To realize the foregoing object, the analogous apparatus is employed within the context of an analogous two-step photoresist layer stripping method, wherein the analogous two-step photoresist layer stripping method employs; (1) a first ultraviolet laser irradiation of the photoresist layer in the presence of a first oxidizing gas composition comprising oxygen to remove from the substrate a bulk portion of the photoresist layer and leave upon the substrate a remainder portion of the photoresist layer; followed by (2) a second ultraviolet laser irradiation of the remainder portion of the photoresist layer in the presence of a second oxidizing gas composition comprising oxygen and ozone to remove the remainder portion of the photoresist layer from the substrate.
Finally, Gordon, in U.S. Pat. No. 5,980,983, discloses a chemical vapor deposition (CVD) method for forming, within fabrications including but not limited to microelectronic fabrications, metal oxide layers while in general avoiding problems associated with conventional solid chemical vapor deposition (CVD) metal source materials when forming the metal oxide layers. To realize the foregoing object, the method employs an admixture of metal beta-diketonate chemical vapor deposition (CVD) metal source materials, which in general are formed as liquid chemical vapor deposition (CVD) metal source materials.
Desirable in the art of microelectronic fabrication are additional methods and materials for forming, with enhanced compositional purity, primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, and derivatives thereof, for use within layers within microelectronic fabrications.
It is towards the foregoing object that the present invention is more generally directed.
A first object of the present invention is to provide a method for forming a metal oxide layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the metal oxide layer is formed with enhanced compositional purity.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention: (1) a method for purifying a metal oxide layer that may be employed within a microelectronic fabrication; and (2) a method for fabricating with enhanced purity a metal oxide layer that may be employed within a microelectronic fabrication.
Within the method for purifying the metal oxide layer, there is first provided a substrate having formed thereover a metal oxide layer, where the metal oxide layer is formed of a metal oxide base material having incorporated therein a concentration of a contaminant material susceptible to reaction with an oxidant to form a volatile contaminant material. There is then positioned the substrate within a reactor chamber and introduced into the reactor chamber the oxidant. There is then irradiated within the reactor chamber the metal oxide layer and the reactant with a radiation source such as to reduce within the metal oxide base material the concentration of the contaminant material and thus form from the metal oxide layer a purified metal oxide layer.
Within the method for forming with enhanced purity the metal oxide layer, there is first provided a reactor chamber. There is then positioned within the reactor chamber a substrate. There is then formed over the substrate within the reactor chamber, while irradiating the substrate within the reactor chamber in the presence of at least one of an oxidant and a metal source material within the reactor chamber with a radiation source, a metal oxide layer, wherein the metal source material has incorporated therein a contaminant material susceptible to reaction with the oxidant to form a volatile contaminant material.
Thus, within the present invention with respect to both: (1) purifying a metal oxide layer; and (2) forming with enhanced purity a metal oxide layer, there is employed an irradiation of either: (1) a metal oxide layer; or (2) a substrate within the presence of at least one of an oxidant and a metal source material, such as to either: (1) reduce a concentration of a contaminant material incorporated within a metal oxide base material from which is formed a metal oxide layer; or (2) inhibit in a first instance formation of a contaminant material within a metal oxide layer.
The methods of the present invention are readily commercially implemented. The present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of specific process limitations to provide the present invention. Since it is thus a specific set of process limitations that provides at least in part the present invention, rather than the existence of methods and materials that provides the present invention, the methods of the present invention are readily commercially implemented.